Accelerating Encryption Algorithms using Impulse C Page 1 Overview Encryption and decryption code that has not been written with hardware compilation in mind can result in less than optimal results when those results are measure in terms of process latencies, data throughput and size of the generated logic. This is because the fundamental target of compilation, in this case an FPGA and its constituent hardware resources, is quite different from a traditional processor, and the C language is by design optimized for processor-based architectures. By using some relatively simple C programming techniques, however, it is possible to dramatically accelerate the performance of many types of algorithms. This white paper presents some of these techniques, using the 3DES (triple DES encryption) algorithm as a basis for discussion. Note: this application note is adapted from Practical FPGA Programming in C by David Pellerin and Scott Thibault, published in 2005 by Pearson. Examining the 3DES example In the Practical FPGA Programming in C, an example of data encryption using the triple-DES encryption algorithm was presented, using a legacy C implementation of the algorithm as a basis for the application. The purpose of this example was to demonstrate how to prototype a hardware implementation in an FPGA, using C code that had previously been written for and compiled to an embedded processor. When hardware simulation of the resulting RTL was performed, it was determined that the rate at which the algorithm could generate encrypted blocks of data was approximately one block approximately every 150 cycles. This is rate that is faster in terms of clock cycles than what could be achieved in a software implementatio...
