Preliminary H27UBG8T2BTR-BC Series 32Gb(4096M x 8bit) Legacy MLC NAND Flash Rev 0.7 / Jan. 20111F26 32Gb MLC NAND Flash MemoryTSOP LegacyH27UBG8T2BTR-BCH27UCG8U5BTR-BCThis document is a general product description and is subject to change without notice. Hynix does not assume any responsibilityfor use of circuits described. No patent licenses are implied.Preliminary H27UBG8T2BTR-BC Series 32Gb(4096M x 8bit) Legacy MLC NAND Flash Rev 0.7 / Jan. 20112Document Title32Gbit(4096M x 8bit) Legacy NAND Flash MemoryRevision HistoryRevision No.HistoryDraft DateRemark0.0Initial DraftOct. 13. 2010 Preliminary0.1 ~ 0.61st ~ 6th internal release Dec. 20. 2010 Preliminary0.7Correct Figure4.Array Organization(Page10)Jan. 03. 2011PreliminaryPreliminary H27UBG8T2BTR-BC Series 32Gb(4096M x 8bit) Legacy MLC NAND Flash Rev 0.7 / Jan. 20113■ Multi Level Cell(MLC) Technology■ NAND Interface- x8 bus width- Multiplexed address/data-Pin-out compatibility for all densities■ Power Supply Voltage- VCC = 2.7 V ~ 3.6 V- VCCQ = 2.7 V ~ 3.6 V / 1.7 V ~ 1.95 V■ Organization- Page size : (8K+640spare)bytes- Block size : (2048K+160K)bytes- Plane size : 1024blocks- Device size : 2048blocks■ Page Read/Program Time- Random Read Time(tR): 90us(MLC), 40us(SLC)- Sequential Access: 20 ns (min.)- Page Program Time: 1300us(MLC), 500us(SLC)- Parallel operations on both planes available,effectively halving program, read and erase time■ Block Erase-Block Erase Time: 3.5ms(Typ.)■ Multi-Plane Architecture- Two independent planes architecture- Parallel operations on both planes available, effectively halving program, read and erase time■ Command Set- ONFI 2.2 Compliant Command Set- Interleaved Copyback Program - Read Unique IDs ■ Package- Package type : TSOP- Chip count :...
