EE 240 Term Project Spring, 2003 Gang Liu Outline: 1. Design Approach and Decisions 2. OTA Schematics 3. Bias Network Schematics 4. Design Process and Equations 5. Performance Summary 6. Simulation Plots 7. Comments and Conclusion Des ign Approach and Decis ions Specification Supply Voltage 3V Close Loop Gain 16 Dynamic Range >=85dB Settling Accuracy <= 10-4 Settling time 100ns Power Dissipation Minimum Process EE240 0.35um technology Process Corners Slow/nominal/fast Choosing the Right Topology Choosing an optimal circuit topology for a given set of specifications is one of the most crucial design steps since this is where the biggest difference can be made in terms of achievable performance of the circuit. And given the time constraints, it is almost impossible to switch to another topology. The first step in this design is to carefully evaluate the trade-offs among candidates, pick the most appropriate topology to design and optimize. As a first step, the specified settling accuracy tell us that the amplifier needs a very high open loop DC gain (A dc) on the order of (gmro)3~4 and loop gain unity-gain bandwidth of 15.47MHz. Besides, the specified dynamic range of 85dB need both small noise factor and high output swing. Realizing such a high Adc narrows available candidates to either two-stage design, or single-stage gain-boosted amplifier, or triple-cascode design. Triple cascode design is first ruled out because its output range is the worst among the candidates (roughly VDD-6Vdsat). Two stage designs have been widely used and are known to be relatively easy to design. Thus it may be optimized more easily (comparing to gain-boosting topology). Also two stage design can achieve very high outpu...
