大量的verilog源代码VIP免费

VerilogHDL程序举例一，基本组合逻辑功能：双向管脚（clockedbidirectionalpin）VerilogHDL:BidirectionalPinThisexampleimplementsaclockedbidirectionalpininVerilogHDL.ThevalueofOEdetermineswhetherbidirisaninput,feedingininp,oratri-state,drivingoutthevalueb.bidir.vmodulebidirec(oe,clk,inp,outp,bidir);//PortDeclarationinputoe;inputclk;input[7:0]inp;output[7:0]outp;inout[7:0]bidir;reg[7:0]a;reg[7:0]b;assignbidir=oe?a:8'bZ;assignoutp=b;//AlwaysConstructalways@(posedgeclk)beginb<=bidir;a<=inp;endendmodule多路选择器（MUX）////-----------------------------------------------------------------------------------//DESCRIPTION:Multiplexer//Codestyle:usedcasestatement//Widthofoutputterminal:8//Numberofterminals:4//Outputenableactive:HIGH//Outputvalueofallbitswhenenablenotactive:0//-----------------------------------------------------------------------------------modulemux(EN,IN0,IN1,IN2,IN3,SEL,OUT);inputEN;input[7:0]IN0,IN1,IN2,IN3;input[1:0]SEL;output[7:0]OUT;reg[7:0]OUT;always@(SELorENorIN0orIN1orIN2orIN3)beginif(EN==0)OUT={8{1'b0}};elsecase(SEL)0:OUT=IN0;1:OUT=IN1;2:OUT=IN2;3:OUT=IN3;default:OUT={8{1'b0}};endcaseendendmodule二进制到BCD码转换//////-----------------------------------------------------------------------------------//DESCRIPTION:BintoBcdconverter//Input(data_in)width:4//Output(data_out)width:8//Enable(EN)active:high//-----------------------------------------------------------------------------------modulebin2bcd(data_in,EN,data_out);input[3:0]data_in;inputEN;output[7:0]data_out;reg[7:0]data_out;always@(data_inorEN)begindata_out={8{1'b0}};if(EN==1)begincase(data_in[3:1])3'b000:data_out[7:1]=7'b0000000;3'b001:data_out[7:1]=7'b0000001;3'b010:data_out[7:1]=7'b0000010;3'b011:data_out[7:1]=7'b0000011;3'b100:data_out[7:1]=7'b0000100;3'b101:data_out[7:1]=7'b0001000;3'b110:data_out[7:1]=7'b0001001;3'b111:data_out[7:1]=7'b0001010;default:data_out[7:1]={7{1'b0}};endcasedata_out[0]=data_in[0];endendendmodule二进制到格雷码转换//-----------------------------------------------------------------------------------//DESCRIPTION:Bintograyconverter//Input(DATA_IN)width:4//Enable(EN)active:high//-----------------------------------------------------------------------------------moduleBIN2GARY(EN,DATA_IN,DATA_OUT);inputEN;input[3:0]DATA_IN;output[3:0]DATA_OUT;assignDATA_OUT[0]=(DATA_IN[0]^DATA_IN[1])&&EN;assignDATA_OUT[1]=(DATA_IN[1]^DATA_IN[2])&&EN;assignDATA_OUT[2]=(DATA_IN[2]^DATA_IN[3])&&EN;assignDATA_OUT[3]=DATA_IN[3]&&EN;endmodule7段译码器//-----------------------------------------------------------------------------------//DESCRIPTION:BINtosevensegmentsconverter//segmentencoding//a//+---+//f||b//+---+<-g//e||c//+---+//d//Enable(EN)active:high//Outputs(data_out)active:low//-----------------------------------------------------------------------------------modulebin27seg(data_in,EN,data_out);input[3:0]data_in;inputEN;output[6:0]data_out;reg[6:0]data_out;always@(data_inorEN)begindata_out=7'b1111111;if(EN==1)case(data_in)4'b0000:data_out=7'b1000000;//04'b0001:data_out=7'b1111001;//14'b0010:data_out=7'b0100100;//24'b0011:data_out=7'b0110000;//34'b0100:data_out=7'b0011001;//44'b0101:data_out=7'b0010010;//54'b0110:data_out=7'b0000011;//64'b0111:data_out=7'b1111000;//74'b1000:data_out=7'b0000000;//84'b1001:data_out=7'b0011000;//94'b1010:data_out=7'b0001000;//A4'b1011:data_out=7'b0000011;//b4'b1100...