VHDL语言设计4选1多路选择器VIP专享VIP免费

4选1多路选择器的VHDL描述要求：THEN语句和CASE语句实现4选1多路选择器，其中选择控制信号s1和s0的数据类型为STD_LOGIC_VECTOR;当s1=‟0‟,s0=‟0‟；s1=‟0‟,s0=‟1‟；s1=‟1‟,s0=‟0‟和s1=‟1‟,s0=‟1‟时,分别执行y<=a、y<=b、y<=c、y<=d。一、解法1：用IF_THEN语句实现4选1多路选择器（1）程序：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux41ISPORT(a,b,c,d:INSTD_LOGIC;s0:INSTD_LOGIC;s1:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux41;ARCHITECTUREif_mux41OFmux41ISSIGNALs0s1:STD_LOGIC_VECTOR(1DOWNTO0);--定义标准逻辑位矢量数据BEGINs0s1<=s1&s0;--s1相并s0,即s1与s0并置操作PROCESS(s0s1,a,b,c,d)BEGINIFs0s1="00"THENy<=a;ELSIFs0s1="01"THENy<=b;ELSIFs0s1="10"THENy<=c;ELSEy<=d;ENDIF;ENDPROCESS;ENDARCHITECTUREif_mux41;(2)编译的结果如下：编译报告：二、解法2：用CASE语句实现4选1多路选择器（1）程序:LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux41ISPORT(a,b,c,d:INSTD_LOGIC;s0:INSTD_LOGIC;s1:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDENTITYmux41;ARCHITECTUREcase_mux41OFmux41ISSIGNALs0s1:STD_LOGIC_VECTOR(1DOWNTO0);--定义标准逻辑位矢量数据类型BEGINs0s1<=s1&s0;--s1相并s0,即s1与s0并置操作PROCESS(s0s1,a,b,c,d)BEGINCASEs0s1IS--类似于真值表的case语句WHEN"00"=>y<=a;WHEN"01"=>y<=b;WHEN"10"=>y<=c;WHEN"11"=>y<=d;WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;ENDcase_mux41;（2）编译结果：编译报告：