March 1, 2005H O L D I N G S C O. L T D .V E R I S I L I C O NClock Gating for Low Power DesignDesign FlowSummaryTitle: Clock Gating for Low Power Design Design FlowDocument Number:Low Power 1.0Issue:SummaryOriginated By: Jasper Hu, Yongliu WangPROPRIETARY INFORMATIONThe information contained in this document is the property of VeriSilicon who owns the copyright therein. Except specifically granted the written consent by Verisilicon, the holder of this document shall keep all information contained herein confidential and shall protect the document from being disclosed or disseminated either wholly or in part to any third party.VeriSilicon Holding Co. Ltd.PROPRIETARYDPHY2.0 USB2.0 PHY Test Chip Design FlowDocument Number: GSDPHY2.0Issue SummaryMarch 1, 20051Filename: Clock Gating FlowTOC.fm1.0Scope....................................................................................................................... 41.1Glossary...............................................................................................................................41.2Related Documents..............................................................................................................42.0Power Assessment...................................................................................................52.1Terminologies......................................................................................................................52.2Power Assessment Flow......................................................................................................52.2.1Power Compiler Flow Diagram............................................................................52.2.2Power Assessment for unannotated Switching Activities.....................................62.2.3Add Power Assessment Related System Tasks to VCS.......................
