基于DDS信号技术的信号发生器的设计VIP免费

基于DDS信号技术的信号发生器的设计直接数字式频率合成技术DDS是新一代的频率合成技术，采用数字控制信号的相位增加技术，具有频率分辨率高，频率切换快，频率切换时相位连续和相位噪声低以及全数字化易于集成等优点而被广泛采用。一．程序代码（1）ADDER32Blibraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityADDER32Bisport(ain:instd_logic_vector(31downto0);bin:instd_logic_vector(31downto0);cout:outstd_logic_vector(31downto0));end;architectureoneofADDER32Bisbegincout<=ain+bin;end;（2）juxing_romLIBRARYieee;USEieee.std_logic_1164.all;LIBRARYaltera_mf;USEaltera_mf.all;ENTITYjuxing_romISPORT(address:INSTD_LOGIC_VECTOR(11DOWNTO0);clock:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDjuxing_rom;ARCHITECTURESYNOFjuxing_romISSIGNALsub_wire0:STD_LOGIC_VECTOR(7DOWNTO0);COMPONENTaltsyncramGENERIC(address_aclr_a:STRING;init_file:STRING;intended_device_family:STRING;lpm_hint:STRING;lpm_type:STRING;numwords_a:NATURAL;operation_mode:STRING;outdata_aclr_a:STRING;outdata_reg_a:STRING;widthad_a:NATURAL;width_a:NATURAL;width_byteena_a:NATURAL);PORT(clock0:INSTD_LOGIC;address_a:INSTD_LOGIC_VECTOR(11DOWNTO0);q_a:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCOMPONENT;BEGINq<=sub_wire0(7DOWNTO0);altsyncram_component:altsyncramGENERICMAP(address_aclr_a=>"NONE",init_file=>"../MIF/juxing.mif",intended_device_family=>"Cyclone",lpm_hint=>"ENABLE_RUNTIME_MOD=NO",lpm_type=>"altsyncram",numwords_a=>4096,operation_mode=>"ROM",outdata_aclr_a=>"NONE",outdata_reg_a=>"CLOCK0",widthad_a=>12,width_a=>8,width_byteena_a=>1)PORTMAP(clock0=>clock,address_a=>address,q_a=>sub_wire0);ENDSYN;（3）mux3_1libraryieee;useieee.std_logic_1164.all;entitymux3_1isport(sin:instd_logic_vector(7downto0);sanjiao,juxing:instd_logic_vector(7downto0);a,b:instd_logic;cout:outstd_logic_vector(7downto0));endmux3_1;architecturebehaviorofmux3_1issignaladdr:std_logic_vector(1downto0);beginprocess(a,b)beginaddr(0)<=a;addr(1)<=b;caseaddriswhen"00"=>cout<=sin;when"01"=>cout<=sanjiao;when"10"=>cout<=juxing;whenothers=>null;endcase;endprocess;endbehavior;（4）sanjiao_romLIBRARYieee;USEieee.std_logic_1164.all;LIBRARYaltera_mf;USEaltera_mf.all;ENTITYsanjiao_romISPORT(address:INSTD_LOGIC_VECTOR(11DOWNTO0);clock:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDsanjiao_rom;ARCHITECTURESYNOFsanjiao_romISSIGNALsub_wire0:STD_LOGIC_VECTOR(7DOWNTO0);COMPONENTaltsyncramGENERIC(address_aclr_a:STRING;init_file:STRING;intended_device_family:STRING;lpm_hint:STRING;lpm_type:STRING;numwords_a:NATURAL;operation_mode:STRING;outdata_aclr_a:STRING;outdata_reg_a:STRING;widthad_a:NATURAL;width_a:NATURAL;width_byteena_a:NATURAL);PORT(clock0:INSTD_LOGIC;address_a:INSTD_LOGIC_VECTOR(11DOWNTO0);q_a:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCOMPONENT;BEGINq<=sub_wire0(7DOWNTO0);altsyncram_component:altsyncramGENERICMAP(address_aclr_a=>"NONE",init_file=>"../MIF/sanjiao.mif",intended_device_family=>"Cyclone",lpm_hint=>"ENABLE_RUNTIME_MOD=NO",lpm_type=>"altsyncram",numwords_a=>4096,operation_mode=>"ROM",outdata_aclr_a=>"NONE",outdata_reg_a=>"CLOCK0",widthad_a=>12,width_a=>8,width_byteena_a=>1)PORTMAP(clock0=>clock,address_a=>address,q_a=>sub_wire0);ENDSYN;（5）sinx256_romLIBRARYieee;USEieee.std_logic_1164.all;LIBRARYaltera_mf;USEaltera_mf.all;ENTITYsinx256_romISPORT(address:INSTD_LOGIC_VECTOR(7DOWNTO0);inclock:INSTD_LOGIC;q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDsinx256_rom;ARCHITECTURESYNOF...