基于FPGA的全数字锁相环的设计摘要伴随当下集成电路体系的迅猛发展，锁相环当下发展为设计集成电路的主要构成，基于此研究其具备显著的现实层面的含义。针对传统类型的锁相环而言，其普遍为数模混合电路，工艺层面其同系统芯片之下的数字电路具备兼容层面的问题，基于此构建同数字电路比较兼容的全数字锁相环（ADPLL）具备一定的价值。构建ADPLL可应用设计数字电路之中的流程，也就是首先编撰了硬件描述语言，此后综合逻辑，基于此对ADPLL具备极强的可进行移植的属性。该文章在对锁相环基本原理描述过程中，归纳论述了全数字锁相环下的相关优势，可以了解到对全数字锁相环而言，其具备很多的优点，出于具备数字的属性，可以很快的对ADPLL进行捕获，基于此对ADPLL而言，特别需要进行分析和研究。按照分析全数字锁相环，实现了其主子模块的构建和确定，设定了诸多的子模块，即鉴相器子模块、K变模可逆计数器子模块、脉冲加减器子模块和分频器子模块，以及设定关键参数的程序，融合该设计下的仿真波形细致的论述了数字锁相环的工作环节。最终出于QuartusII仿真平台针对锁相环其在FPGA中落实波形仿真，其证明构建的锁相环，具备优良的性能，可更好的契合预期成效。关键词：FPGA；锁相环；子模块；QuartusII；波形仿真IABSTRACTWiththerapiddevelopmentofthecurrentintegratedcircuitsystem,thephase-lockedloophasnowevolvedintothemaincomponentofthedesignofintegratedcircuits.Basedonthisresearch,ithasasignificantrealisticlevel.Forthetraditionaltypeofphase-lockedloop,itisgenerallyadigital-analoghybridcircuit.Attheprocesslevel,ithasthecompatibilitylevelproblemwiththedigitalcircuitunderthesystemchip.Basedonthis,anall-digitalphase-lockedloopcompatiblewiththedigitalcircuitisconstructed.ADPLL)hasacertainvalue.TheconstructionoftheADPLLcanbeappliedtotheflowofdesigningdigitalcircuits,thatis,thehardwaredescriptionlanguageisfirstcompiled,andthentheintegratedlogicisbasedontheextremelyportablenatureoftheADPLL.Intheprocessofdescribingthebasicprincipleofthephase-lockedloop,thispapersummarizestherelatedadvantagesundertheall-digitalphase-lockedloop.Itcanbeunderstoodthatfortheall-digitalphase-lockedloop,ithasmanyadvantages,fortheattributewithnumbers.TheADPLLcanbecapturedveryquickly,basedonwhichanalysisandresearchisparticularlyneededfortheADPLL.Accordingtotheanalysisoftheall-digitalphase-lockedloop,theconstructionanddeterminationofitsmainsub-moduleisrealized,andmanysub-modulesareset,namelythephasedetectorsub-module,theK-modulereversiblecountersub-module,thepulseadder-subtractersub-moduleandthefrequencydivision.Thesub-module,aswellastheprogramforsettingkeyparameters,combinesthesimulationwaveformsofthedesigntodiscusstheworkingphaseofthedigitalphase-lockedloop.Finally,theQuartusIIsimulationplatformimplementswaveformsimulationintheFPGAforthephase-lockedloop,whichprovesthattheconstructedphase-lockedloophasexcellentperformanceandcanbettermeettheexpectedresults.IIKeywords:FPGA;phase-lockedloop;sub-module;QuartusII;waveformsimulationIII黑龙江工程学院本科生毕业设计目录摘要························································································IAbstract···················································································II第1章引言·············································································11.1选题的目的意义·····...
