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JEDECSTANDARDStress-Test-DrivenQualificationofIntegratedCircuitsIC集成电路压力测试考核JESD47I(RevisionofJESD47H.01,April2011)JULY2012JEDECSOLIDSTATETECHNOLOGYASSOCIATIONNOTICEJEDECstandardsandpublicationscontainmaterialthathasbeenprepared,reviewed,andapprovedthroughtheJEDECBoardofDirectorslevelandsubsequentlyreviewedandapprovedbytheJEDEClegalcounsel.JEDECstandardsandpublicationsaredesignedtoservethepublicinterestthrougheliminatingmisunderstandingsbetweenmanufacturersandpurchasers,facilitatinginterchangeabilityandimprovementofproducts,andassistingthepurchaserinselectingandobtainingwithminimumdelaytheproperproductforusebythoseotherthanJEDECmembers,whetherthestandardistobeusedeitherdomesticallyorinternationally.JEDECstandardsandpublicationsareadoptedwithoutregardtowhetherornottheiradoptionmayinvolvepatentsorarticles,materials,orprocesses.BysuchactionJEDECdoesnotassumeanyliabilitytoanypatentowner,nordoesitassumeanyobligationwhatevertopartiesadoptingtheJEDECstandardsorpublications.TheinformationincludedinJEDECstandardsandpublicationsrepresentsasoundapproachtoproductspecificationandapplication,principallyfromthesolidstatedevicemanufacturerviewpoint.WithintheJEDECorganizationthereareprocedureswherebyaJEDECstandardorpublicationmaybefurtherprocessedandultimatelybecomeanANSIstandard.Noclaimstobeinconformancewiththisstandardmaybemadeunlessallrequirementsstatedinthestandardaremet.Inquiries,comments,andsuggestionsrelativetothecontentofthisJEDECstandardorpublicationshouldbeaddressedtoJEDECattheaddressbelow,orrefertojodec.orgunderStandardsandDocumentsforalternativecontactinformation.Publishedby©JEDECSolidStateTechnologyAssociation20123103North10thStreetSuite240SouthArlington,VA22201-2107Thisdocumentmaybedownloadedfreeofcharge;howeverJEDECretainsthecopyrightonthismaterial.Bydownloadingthisfiletheindividualagreesnottochargefororreselltheresultingmaterial.PRICE:ContactJEDECPrintedintheU.S.A.AllrightsreservedJEDECStandardNo.47IPage55.5Devicequalificationrequirements(cont’d)STRESSDRIVENQUALIFICATIONOFINTEGRATEDCIRCUITSIC集成电路压力测试考核(FromJEDECBoardBallot,JCB-12-24,formulatedunderthecognizanceoftheJC14.3SubcommitteeonSiliconDevicesReliabilityQuali^cationandMonitoring.)通过JEDEC委员会JCB-12-24号投票，在JC14.3硅晶圆器件可靠性考核和监控小组委员会审理后系统地阐述和制定1Scope范围Thisstandarddescribesabaselinesetofacceptancetestsforuseinqualifyingelectroniccomponentsasnewproducts,aproductfamily,orasproductsinaprocesswhichisbeingchanged.这个文档描述了用于考核新产品、同族器件或工艺变更的可接受的基准测试标准Thesetestsarecapableofstimulatingandprecipitatingsemiconductordeviceandpackagingfailures.Theobjectiveistoprecipitatefailuresinanacceleratedmannercomparedtouseconditions.FailureRateprojectionsusuallyrequirelargersamplesizesthanarecalledoutinqualificationtesting.Forguidanceonprojectingfailurerates,re命rtoJESD85MethodsforCalculatingFailureRatesinUnitsofFITs.Thisqualificationstandardisaimedatagenericqualificationforarangeofuseconditions,butisnotapplicableatextremeuseconditionssuchasmilitaryapplications,automotiveunder-the-hoodapplications,oruncontrolledavionicsenvironments,nordoesitaddress2ndlevelreliabilityconsiderations,whichareaddressedinJEP150.Wherespeci^cuseconditionsareestablished,quali^cationtestingtailoredtomeetthosespeci^crequirementscanbedeveloped,usingJESD94thatwillresultinabetter...