实验四：8位加法器设计实验1.实验目的：熟悉利用quartus原理图输入方法设计简单组合电路，掌握层次化设计方法。2.实验原理：一个八位加法器可以由八个全加器构成，加法器间的进位可以串行方式实现，即将低位加法器的进位输出cout与相邻的高位加法器的最低进位输入信号cin相接。3.实验任务：完成半加器，全加器，八位加法器设计，使用例化语句，并将其设计成一个原件符号入库，做好程序设计，编译，程序仿真。1）编译成功的半加器程序：moduleh_adder(a,b,so,co);inputa,b;outputso,co;assignso=a^b;assignco=a&b;endmodule2）编译成功的全加器程序：modulef_adder(ain,bin,cin,cout,sum);outputcout,sum;inputain,bin,cin;wirenet1,net2,net3;h_adderu1(ain,bin,net1,net2);h_adderu2(.a(net1),.so(sum),.b(cin),.co(net3));oru3(cout,net2,net3);endmodule3）编译成功的八位加法器程序：modulef_adder8(ain,bin,cin,cout,sum);output[7:0]sum;outputcout;input[7:0]ain,bin;inputcin;wirecout0,cout1,cout2,cout3,cout4,cout5,cout6;f_adderu0(.ain(ain[0]),.bin(bin[0]),.cin(cin),.sum(sum[0]),.cout(cout0));f_adderu1(.ain(ain[1]),.bin(bin[1]),.cin(cout0),.sum(sum[1]),.cout(cout1));f_adderu2(.ain(ain[2]),.bin(bin[2]),.cin(cout1),.sum(sum[2]),.cout(cout2));f_adderu3(.ain(ain[3]),.bin(bin[3]),.cin(cout2),.sum(sum[3]),.cout(cout3));f_adderu4(.ain(ain[4]),.bin(bin[4]),.cin(cout3),.sum(sum[4]),.cout(cout4));f_adderu5(.ain(ain[5]),.bin(bin[5]),.cin(cout4),.sum(sum[5]),.cout(cout5));f_adderu6(.ain(ain[6]),.bin(bin[6]),.cin(cout5),.sum(sum[6]),.cout(cout6));f_adderu7(.ain(ain[7]),.bin(bin[7]),.cin(cout6),.sum(sum[7]),.cout(cout));endmodule4）八位加法器仿真程序：modulef_adder8_vlg_tst();//constants//generalpurposeregisters//regeachvec;//testvectorinputregistersreg[7:0]ain;reg[7:0]bin;regcin;//wireswirecout;wire[7:0]sum;//assignstatements(ifany)f_adder8i1(//portmap-connectionbetweenmasterportsandsignals/registers.ain(ain),.bin(bin),.cin(cin),.cout(cout),.sum(sum));initialbeginain=10;bin=11;cin=0;#100ain=10;bin=10;cin=0;#100ain=10;bin=10;cin=1;#100ain=12;bin=18;cin=0;#100ain=12;bin=18;cin=1;#100$stop;endendmodule5）八位加法器仿真图：6）元件原理图及元件入库：半加器原理图：文件入库bsf：全加器原理图：全加器元件入库：八位全加器rtl图：八位全加器仿真图：
