Allegro线宽、间距、等长、差分

Allegro 中的约束规则设置Allegrophan刚好五个字www.pcbbbs.com修订记录日期版本描述作者2008-12V1.0初版，学完的总结。适用于Cadence15.5版本。Allegrophan2009-09-08V1.1小改，修改部分措辞Allegrophan2009-10-14V1.2小改，更正、修改几个错漏之处。添加一些说明性文字。感谢群里的佳猪、梦姑娘等朋友的指正！Allegrophanwww.pcbbbs.com目录一：Physical（Line/vias）rule物理特性（线宽和过孔）约束设置：.............41）“Setvalues”设置约束特征值....................................................................52）“Attachproperty”绑定约束.....................................................................63）“Assignmenttable”约束规则分配........................................................8二 “Spacingrule”间距约束设置...........................................................................91）“Setvalues”设置约束特征值................................................................92）“Attachproperty”绑定约束.................................................................103）“Assignmenttable”约束规则分配......................................................11三 Constraintareas区域约束设置......................................................................12四 Allegro中走线长度的设置............................................................................131）差分线等长设置......................................................................................132）一组 Net等长..........................................................................................163）XNet等长................................................................................................17www.pcbbbs.com线宽、线距、区域的约束主要在“ConstraintsSys”中设置，点击“Setup/Constraints”或点击图标打开“ConstraintsSys”窗口，如下：“ConstraintsSys”窗口分两个级别，第一级别有两类：Standarddesign rules 和 ExteExtendedndeddesign rules。Standarddesignrules仅有一级分类，点击“Set standardvalues”设置默认约束值，如下：默认约束设置线宽约束设置间距约束设置区域约束设置www.pcbbbs.com这里可...