基于FPGA的数字钟设计（VHDL语言实现）

基 于 FPGA 的 数 字 钟 设 计（ VHDL语 言 实 现 ）下载后可任意编辑摘要本设计采纳EDA 技术，以硬件描述语言VHDL为系统逻辑描述手段设计文件，在MaxplusII 工具软件环境下，采纳自顶向下的设计方法，由各个基本模块共同构建了一个基于FPGA 的数字钟。芯片采纳EP1K100QC208-3 ，由时钟模块、控制模块、计时模块、数据译码模块、显示以及报时模块组成。经编译和仿真所设计的程序，在可编程逻辑器件上下载验证，本系统能够完成年、月、日和时、分、秒的分别显示，由按键输入进行数字钟的校时、清零、启停功能。关键词 数字钟；硬件描述语言；VHDL；FPGA ；键盘接口2下载后可任意编辑AbstractThe design for a multi-functional digital clock, with a year, month, day, hours, minutes and seconds count display to a 24-hour cycle count; have proof functions and the whole point timekeeping function. The use of EDA design technology, hardware-description language VHDL description logic means for the system design documents, in MaxplusII tools environment, a top-down design, by the various modules together build a FPGA-based digital clock.The main system chips used EP1K100QC208-3, make up of the clock module, control module, time module, data decoding module, display and broadcast module. After compiling the design and simulation procedures, the programmable logic device to download verification, the system can complete the year, month, day and the hours, minutes and seconds respectively, using keys to modify, cleared , start and stop the digital clock. Keywords digital clock; hardware description language; VHDL; FPGA; keyboard interface3下载后可任意编辑目录1 绪 论 .....................................................................................11.1 选 题 背 景 ............................................................ 11.1.1 课 题 相 关 技 术 的 进 展 ..................21.1.2 课 题 讨 论 的 必 要 性 .........................21.2 课 ...