基于FPGA的2DPSK信号产生器的设计VIP专享

基于 FPGA 的 2DPSK 信号产生器的设计摘 要：随着时代的进步，FPGA 的应用也越来越广泛，FPGA 用硬件描述语言（Verilog HDL）来实现 2DPSK 信号的调制系统，不仅简单方便，而且还能满足现代设备快速、准确、功耗低的特点。Verilog 语言有着灵活多样的电路描述风格，语言功能性强，并且简单易学，这些优良的性能使其得到广泛流行。数字通信技术与 FPGA 的结合是现代通信系统进展的一个必定趋势。FPGA 实现 2DPSK 信号可用如下方法，先通过 FPGA 产生时钟信号，经过分频器产生两路时钟，一路用于基带码的产生，也就是用于驱动 M 序列信号发生器产生绝对码，另一路用于采样正弦信号。M 序列产生的绝对码经过差分运算转换成相对码，再把相对码加到正弦信号上输出，这就相当于对原码进行了调相输出。而 FPGA 只能处理数字信号，因此要经过 DAC 器件转换为模拟信号，从而产生 2DPSK 信号。通过对仿真波形的分析可知，该方案很好的实现了 2DPSK 信号产生器的功能。关键词：FPGA；Verilog HDL；2DPSK 信号产生器；数字调制；串并转换；Design of 2DPSK Signal Generator Based on FPGAI下载后可任意编辑Abstract：With the progress of the times, FPGA is used more and more popularly. FPGA used hardware description language ( Verilog HDL ) to achieve the 2DPSK signal modulation system. It's not only simple and convenient, but also equipped with many excellent characteristics of modern devices, such as fast, accurate, low power consumption. Verilog language can descript circuit variously and flexibly, and has powerful function. What’s more, it’s easy to learn for us. These excellent properties make Verilog language applied widely. The combination of digital communication technology and FPGA is a certainly trend of the development of modern communication system. The process of producing 2DPSK signal by FPGA is as follows. The clock signal generated by FPGA will generate two signals with different frequency. One is used to sampling, the other is to drive M array signal generator. It will...