A20 User Manual (Revision 1.0) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 240 / 835 1.19. Port Controller 1.19.1. Port Description The chip has several ports for multi-functional input/out pins. They are shown below: Port A(PA): 18 input/output port Port B(PB): 24 input/output port Port C(PC): 25 input/output port Port D(PD): 28 input/output port Port E(PE) : 12 input/output port Port F(PF) : 6 input/output port Port G(PG) : 12 input/output port Port H(PH) : 28 input/output port Port I(PI) : 22 input/output port Port S(PS) : 84 input/output port for DRAM controller For various system configurations, these ports can be easily configured by software. All these ports (except PS) can be configured as GPIO if multiplexed functions not used. 32 external PIO interrupt sources are supported and interrupt mode can be configured by software. Confidential A20 User Manual (Revision 1.0) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 241 / 835 1.19.2. Port Configuration Table Port A(PA) Multiplex Function Select PA0 ERXD3 SPI1_CS0 UART2_RTS GRXD3 PA1 ERXD2 SPI1_CLK UART2_CTS GRXD2 PA2 ERXD1 SPI1_MOSI UART2_TX GRXD1 PA3 ERXD0 SPI1_MISO UART2_RX GRXD0 PA4 ETXD3 SPI1_CS1 GTXD3 PA5 ETXD2 SPI3_CS0 GTXD2 PA6 ETXD1 SPI3_CLK GTXD1 PA7 ETXD0 SPI3_MOSI GTXD0 PA8 ERXCK SPI3_MISO GRXCK PA9 ERXERR SPI3_CS1 GNULL/ERXERR I2S1_MCLK PA10 ERXDV UART1_TX GRXCTL/RXDV PA11 EMDC UART1_RX GMDC PA12 EMDIO UART6_TX UART1_RTS GMDIO PA13 ETXEN UART6_RX UART1_CTS GTXCTL/ETXEN PA14 ETXCK UART7_TX UART1_DTR GNULL/ETXCK I2S1_BCLK PA15 ECRS UART7_RX UART1_DSR GTXCK/ECRS I2S1_LRCK PA16 ECOL CAN_TX UART1_DCD GCLKIN/ECOL I2S1_DO PA17 ETXERR CAN_RX UART1_RING GNULL/ETXERR I2S1_DI Port A(PA) Multiplex...
