精品文档---下载后可任意编辑Computer organization and architectureMidterm exam2024/11I
Multi-choice1
Erasure unit for flash memory is(B)a
Chip levelb
byte levelc
block leveld
word level2
Cache usually adopts (B)a
Direct access method (semi sequential)b
random access methodc
Sequential access methodd
read only method3
If memory cycle is 250ns and 16 bits are read each time, then the data transfer rate of the memory is (d)a
4x106 bytes/sb
4M bytes/sc
8x106 bytes/sd
8M bytes/s4
假设某系统总线在一个总线周期中并行传输 4 字节信息, 一个总线周期占用2 个时钟周期, 总线时钟频率为 10MHz, 则总线带宽是( b )a
10 MB/sb
20 MB/sc
40 MB/sd
80 MB/s5
浮点数加、减运算过程包括对阶、尾数运算、规格化、舍入和判溢出等步骤
设浮点数的阶码和尾数均采纳补码表示,且位数分别为 5 位和 7 位(均含 2位符号位)
若有两个数 X=27x29/32,Y=25x5/8,则用浮点加法计算 X+Y 的最终结果是( d ) a
00111 1100010b
00111 0100010 c
01000 0010001d
设某浮点数共 12 位, 其