高效率同步降压型转换器的版图设计研究_初版VIP免费

摘要随着集成电路已经进入深亚微米时代，版图设计早已成为集成电路产业链中重要的一环。它不仅是芯片是否能被生成的保证，同时也关系到实际产品的性能是否能满足预期的目标。因此，同步降压型转换器的版图设计研究具有非常重要的意义。该芯片是一个高频率，同步整流，降压型开关模式转换器。具有内置的功率MOS，实现了连续输出2A电流，具有优异的负载和电路调控能力。在很宽的输入电压范围，该芯片具有同步操作模式，在保证输出电流效率更高的范围内，电流模式能提供快速的瞬态响应和简化环路稳定性。该芯片具有完整的保护功能，如过电流保护和热关机。该芯片采用的是节省空间的SOT23-8引脚封装。关键词：高效率，同步整流，电流模式ABSTRACTWiththeintegratedcircuithasenteredthedeepsub-microntimes,thelayoutdesignhadbecameanimportantpartoftheintegratedcircuitindustrychain.Itisnotonlythechipcanbegenerated,butalsorelatedtowhethertheactualproductperformancecanachievetheexpectedtarget.Thereforce,itisveryimportanttoresearchlayoutdesignofthesynchronousandstep-downconverter.Thischipisahigh-frequency,synchronous,rectified,step-down,switch-modeconverterwithbuilt-inpowerMOSFETs.Itoffersaverycompactsolutiontoachievea2Acontinuousoutputcurrentwithexcellentloadandlineregulationoverawideinputsupplyrange.TheMP1494hassynchronousmodeoperationforhigherefficiencyovertheoutputcurrentloadrange.Current-modeoperationprovidesfasttransientresponseandeasesloopstabilization.Fullprotectionfeaturesincludeover-currentprotectionandthermalshutdown.TheMP1494requiresaminimalnumberofreadily-availablestandardexternalcomponents,andisavailableinaspace-saving8-pinpackage.Keywords：high-frequency,synchronousrectifier,currentmode目录第1章．课题整体框架...........................................................................................11.1课题任务..................................................................................................................11.2课题要求..................................................................................................................11.3研究意义..................................................................................................................2第2章．设计方案...................................................................................................32.1软件部分..................................................................................................................32.1.1软件工具...............................................................................................................32.1.2cadence操作说明.................................................................................................32.2集成电路版图可靠性需要避免的三大效应..........................................................72.2.1PAE........................................................................................................................72.2.2Latch_up................................................................................................................82.2.3ESD效应.............................................................................................................112.3子模块版图............................................................................................................142.3.1LDO模块............................................................................................................142.3.2UVLO模块..............................................................