1.General descriptionThe LPC3220/30/40/50 embedded microcontrollers were designed for low power, highperformance applications. NXP achieved their performance goals using a 90 nanometerprocess to implement an ARM926EJ-S CPU core with a vector floating point co-processorand a large set of standard peripherals including USB On-The-Go. TheLPC3220/30/40/50 operates at CPU frequencies of up to 266 MHz.The NXP implementation uses a ARM926EJ-S CPU core with a Harvard architecture,5-stage pipeline, and an integral Memory Management Unit (MMU). The MMU providesthe virtual memory capabilities needed to support the multi-programming demands ofmodern operating systems. The ARM926EJ-S also has a hardware based set of DSPinstruction extensions, which includes single cycle MAC operations, and hardware basednative Jazelle Java Byte-code execution. The NXP implementation has a 32 kB instructioncache and a 32 kB data cache.For low power consumption, the LPC3220/30/40/50 takes advantage of NXP’s advancedtechnology development to optimize intrinsic power and uses software controlledarchitectural enhancements to optimize application based power management.The LPC3220/30/40/50 also includes 256 kB of on-chip static RAM, a NAND flashinterface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and anexternal bus interface that supports SDR and DDR SDRAM as well as static devices. Inaddition, the LPC3220/30/40/50 includes a USB 2.0 full-speed interface, seven UARTs,two I2C-bus interfaces, two SPI/SSP ports, two I2S-bus interfaces, two single outputPWMs, a motor control PWM, six general purpose timers with capture inputs andcompare outputs, a Secure Digital (SD) interface, and a 10-bit Analog-to-Digital Converter(ADC) with a touch screen...
