DDR3LayoutDesignVIP专享

Freescale SemiconductorApplication Note© Freescale Semiconductor, Inc., 2010. All rights reserved. The design guidelines presented in this application note apply to products that leverage the DDR3 SDRAM IP core, and they are based on a compilation of internal platforms designed by Freescale Semiconductor, Inc. The purpose of these guidelines is to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer.Freescale highly recommends that the system/board designer verify all design aspects (signal integrity, electrical timings, and so on) through simulation before PCB fabrication.Document Number: AN3940Rev. 1, 03/2010Contents1. Designer Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . 22. Termination Dissipation . . . . . . . . . . . . . . . . . . . . . . . 73. VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74. VTT Voltage Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85. Layout Guidelines for the Signal Groups . . . . . . . . . . 86. Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127. Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Hardware and Layout Design Considerations for DDR3 SDRAM Memory InterfacesbyNetworking and Multimedia GroupFreescale Semiconductor, Inc.Austin, TXHardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces, Rev. 12Freescale Semiconductor Designer Checklist1Designer ChecklistIn the follow ing checklist, s...