JEDEC Standard No. 21CPage 4.20.18-1Revision 1.1Release 204.20.18 - 204-Pin DDR3 SDRAM Unbuffered SO-DIMM Design SpecificationPC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 Unbuf-fered SO-DIMM Reference Design SpecificationRevision 1.1April 2010JEDED Standard No. 21CPage 4.20.18-2Release 20Revision 1.11 Product Description ......................................................................................................................72 Environmental Requirements........................................................................................................93 Architecture...................................................................................................................................94 Component Details......................................................................................................................184.1 DDR3 SDRAM FBGA Component Specifications................................................................. 214.2 Reference SPD and Temp Sensor Component Specifications.................................................215 Unbuffered SO-DIMM Details................................................................................................... 225.1 DDR3 SO-DIMM Gerber File Releases.................................................................................. 236 SO-DIMM Wiring Details.......................................................................................................... 266.1 Signal Groups...........................................................................................................................266.2 General Net Structure Routing Guidelines.............................................................................. 266.3 Explanation of Net Structure Diagrams................................................................................... 266.4 Clock Control and Address/Command Groups................
