DDR3硬件设计和Layout设计[中为电子科技工作室.]

爱手册爱翻译 中为电子科技 1 / 13 DDR3 硬件设计和Layout 设计 译自 飞思卡尔官方文档 Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces Document revision history Date Revision Changes 2015-03-29 1.0 第一次撰稿 爱手册爱翻译 中为电子科技 2 / 13 目录 1 设计检查表 ................................................................................................................................. 3 2 终端匹配电阻功耗计算 ............................................................................................................. 8 3 VREF ............................................................................................................................................ 8 4 VTT 电压轨 ................................................................................................................................. 8 5 DDR 布线 .................................................................................................................................... 9 5.1 数据线 — MDQ[0:63], MDQS[0:8], MDM[0:8], MECC[0:7] .......................................... 9 5.2 Layout 建议 .................................................................................................................. 10 6 仿真 .......................................................................................................................................... 12 7 扩展阅读................................................................................................................................... 13 8 历史版本................................................................................................................................... 13 9 声明 .......................................................................................................................................... 13 爱手册爱翻译 中为电子科技 3 / 13 这是一篇关于DDR3 SDRAM IP core 的设计向导，出自飞思卡尔，...