本科毕业论文（设计、创作）题 目： 全数字锁相环的讨论与设计 全数字锁相环的讨论与设计摘 要本文主要描述了一种设计一阶全数字锁相环的方法，首先分析了课题讨论的意义、锁相环的进展历程讨论现状，然后描述了全数字锁相环的各个组成部件，并且详细分析了锁相环鉴相器、变模可逆计数器、加减脉冲电路、除 H 计数器和除 N 计数器各个模块的工作原理。接着我们使用了 VHDL 语句来完成了鉴相器、数字滤波器和数字振荡器的设计，并且分别使用仿真工具 MAX＋plus II 逐个验证各个模块的功能。最后，将各个模块整合起来，建立了一个一阶全数字锁相环的电路，利用仿真工具 MAX＋plus II 验证了它的功能的能否实现，仿真结果与理论分析基本符合。关键词：全数字锁相环；VHDL；数字滤波器；数字振荡器；锁定时间Design and research of ALL Digital Phase-Locked LoopAbstract In this brief, we presented a way of designing a first-order ALL Digital Phase-Locked Loop (ADPLL) first analyzes the significance of research, the development course of phase-locked loop current research status, and then describes the component parts of all digital phase-locked loop, and detailed analysis of the phase lock loop phase discriminator, reversible counter change mould, add and subtract pulse circuit, in addition to H counter and divide N working principle of each module. Then we use the VHDL statements to complete the phase discriminator, digital filter and the design of the digital oscillator, and using the simulation tool of MAX + plus II one by one to verify the function of each module. Finally, the various modules together, established a first-order digital phase-locked loop circuit, using the simulation tool of MAX + plus II verify the realization of its function, the simulation results and principleKeywords: All Digital Phase-Locked Loop; VHDL; Digital filter; Digital oscillator, Locking time目 录1 引言（绪论）…………………………………………………………………… 5...
