单片机--max-ii-cpld系列概述及应用—-毕业论文设计VIP专享

MAX II CPLD: Lowest Power, Lowest Cost CPLD Family Ever Altera's MAX® II family of CPLD family are the lowest power, lowest cost CPLDs ever. MAX II CPLD family is based on a groundbreaking architecture that delivers the lowest power and the lowest cost per I/O pin of any CPLD family. With the introduction of the MAX IIZ CPLD, there are now three variants that all use the same innovative CPLD architecture: MAX II CPLD MAX IIG CPLD MAX IIZ CPLD This instant-on, non-volatile CPLD family targets general-purpose, low-density logic and portable applications, such as cellular handset design. In addition to delivering the lowest cost for traditional CPLD designs, the MAX II CPLD drives power and cost improvements to higher densities, enabling you to use a MAX II CPLD in place of a higher power or higher cost ASSP or and standard-logic CPLD. Advanced CPLD features The MAX II CPLD enables a high level of functional integration to reduce system design costs. This section describes the advanced features found in every MAX II CPLD. Low power CPLD One-tenth the power consumption (compared to a previous-generation 3.3-V MAX CPLD) 1.8-V core voltage for reduced power consumption and increased reliability CPLD industry's lowest standby specification, allowing longer use in battery powered applications Auto start/stop capability for turning off the CPLD when not in use Cost-optimized architecture Four times the density at half the price (compared to previous MAX CPLD generations) Designed for minimum die size, giving the lowest cost per I/O pin in the industry High performance Support for internal clock frequency rates of up to 300 MHz Twice the performance (compared to a 3.3-V MAX CPLD) ...