摘要采纳自上向下的设计方法,设计了基于复杂可编程逻辑器件的数字频率计。以AT89C51 单片机作为系统的主控部件，完成电路的测试信号控制、数据运算处理、键 盘 扫 描 和 控 制 数 码 管 显 示 。 用 VHDL 语 言 编 程 ， 由 CPLD(Complex Programmable Logic Device)完成各种时序控制及计数功能。该系统具有结构紧凑、可靠性高、测频范围宽和精度高等特点。 关键词 可编程逻辑器件 CPLD 等精度测量法 单片机 VHDL AbstactWith the adoption of the top-down design method and AT89C51 SCMC (Single Chip Mico Computer) as the master control component of the system,the circuit test signalcontrolling,data operation processing,keyboard scanning,and nixie tube display as well were completed by the digital cymometer.A CPLD programmed by VHDL,realized various sequence control and count functions.The system is characterized by impact structure,high reliability,high precision,and wide frequency-test-range. Key Words programmable logic component CPLD measures mensuration single chip mico computer VHDL 目录摘要…………………………………………………………………………………….英文摘要……………………………………………………………………………….绪论…………………………………………………………………………………….Ⅰ第一章 设计方案选择………………………………………………………………….11.1 频率测量模块………………………………………………………………………11.2 周期测量模块………………………………………………………………………31.3 脉冲宽度测量模块…………………………………………………………………41.4 占空比测量模块……………………………………………………………………41.5 标准频率发生电路…………………………………………………………………41.6 小信号处理部分……………………………………………………………………4第二章 基本测量原理与理论误差分析……………………………………………….62.1 等精度频率/周期测量技术………………………………………………………...62.2 预置门时间信号与闸门时间信号……………………………………...
