河南科技大学本科毕业设计（论文《》基于 FPGA 抢答器设计基于 FPGA 扌仓答器设计摘要一本文介绍了一个实行 EDA 技术，基于 FPGA 并在 Qualtusll 工具软件环境下使用 Veni。g 硬件描述语言编写数码管显示 4 路抢答器电路设计．此次设计抢答器能够同时供给 4 位选手或者 4 个代表队进行抢答竞赛，分别使用 4 个按钮a，b，c，d 表示。同时需要设置系统复位和抢答控制开关，这需由主持人控制。主持人在允许抢答情况下，计时器开始从 30s 开始倒计时，直到有些人抢答成功后，由锁存器将时间锁存住，此时数码管上将显示剩下时间及抢答成功选手号码，同时对应选手 LED 灯也被点亮。在推断选手是否回答正确后，由主持人控制加减按钮进行给分。在一轮竞赛结束后，主持人按下复位按钮，则除了计分模块外，其余模块都复位为初始时刻，为下一轮竞赛做好准备。系统芯片主要实行 EP2C8Q208，由抢答判别模块，计时模块，分频器模块，计分模块，锁存器模块，数码管驱动模块组成：经过编译及其仿真所设计程序，该设计抢答器基本能够实现此次设计要求，从而完成了抢答器应具备功效。关键词．抢答器，数码显示，硬件描述语言可编程逻辑门阵列FPGA-BASED RESPONDER DESIGNABSTRACTThis article introduces the design of 4 answeLing device cucuit using an EDA technology Verilog HDL language in FPGA and Quartus Il envuonment.At the same time,the 4 answering device cucult IS displayed by the digital,The Responder can also supply four players or four teams to answer in the game, respectively, using four buttons a, b, c, d. Setting reset and answer 111 a system control switch, which controls required by the moderator. When the moderator allows to answer, the timer starts counts down from the 30s until someone answers successfully, by the time the latch latches will to live, then the remaining time and the number of the player who responds successfully will be displayed on the digital tube, at the same time the LED of the coryesponding player lights will be lighted. Detennined whether the contestant answeys conectly, ...
