SDRAM 64Mb H-die (x 4, x 8, x 16)CMOS SDRAMRev. 1.4 November 2003* Samsung Electronics reserves the right to change products or specification w ithout notice.Revision 1.4November 200364Mb H-die SDRAM SpecificationSDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.4 November 2003Revision HistoryRevision 0.0 (May, 2003) • Target spec releaseRevision 0.1 (July, 2003) • Preliminary spec releaseRevision 0.2 (August, 2003) • Modified IBIS characteristic.Revision 1.0 (September, 2003) • FinalizedRevision 1.1 (September, 2003) • Corrected IBIS Specification.Revision 1.2 (October, 2003) • Deleted speed 7C at x4/x8.Revision 1.3 (October, 2003) • Deleted AC parameter notes 5. Revision 1.4 (November, 2003) • Modified Pin Function description.SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.4 November 2003Part No.OrgainizationMax Freq.InterfacePackage K4S640432H-TC(L)7516Mb x 4 133MHz(CL=3)LVTTL54pin TSOP(II) K4S640832H-TC(L)758Mb x 8 133MHz(CL=3) K4S641632H-TC(L)604Mb x 16166MHz(CL=3) K4S641632H-TC(L)70143MHz(CL=3) K4S641632H-TC(L)75133MHz(CL=3) The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high perfor-mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possibleon every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device tobe useful for a variety of high bandwidth, high performance memory system applications.• JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address• Four banks operation • MRS cycle...
