UART IP Core Specification Au thor: Jacob Gorban gorban@opencores.org Rev. 0.6 August 11, 2002 This page has been intentionally left blankOpenCores UART16550 core specifications 8/11/2002 www.opencores.org Rev 0.6 i Revision History Rev. Date Author Description 0.1 Jacob Gorban First Draft 0.2 27/5/01 Jacob Gorban Added reset values and other changes. 0.3 23/6/01 Jacob Gorban Divisor latch is 16-bit wide update 0.4 17/08/01 Jacob Gorban Modified port names 0.5 03/12/01 Jacob Gorban LSR bits 5,6 clear conditions fixed. In IIR, THRE was fixed. Debug registers were added to Registers. Debug interface was added to Operation. WISHBONE interface ports width modified and wb_sel_i signal is added to the list. 0.6 11/08/02 Jacob Gorban Added optional BAUD_O output OpenCores UART16550 core specifications 8/11/2002 www.opencores.org Rev 0.6 ii Contents Introduction … … … … … … … … … … … … … … … … … … 1 IO ports … … … … … … … … … … … … … … … … … … 2 Clocks … … … … … … … … … … … … … … … … … … 3 Registers … … … … … … … … … … … … … … … … … … 4 Operation … … … … … … … … … … … … … … … … … … 13 Architecture … … … … … … … … … … … … … … … … … … 15OpenCores UART16550 core specifications 8/11/2002 www.opencores.org Rev 0.6 1 of 16 1 Introdu ction The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with modem or other external devices, like another computer using a serial cable and RS232 protocol. This core is designed to be maximally compatible with the industry standard National Semiconductors’ 16550A d...
