顶层代码` include "timescale.v" module aes_top(clk, rst, kld, sel,ld, done, key, text_in, text_out ); input clk, rst; input kld, ld,sel; output done; input [127:0] key; input [127:0] text_in; output [127:0] text_out; reg[31:0] wk0, wk1, wk2, wk3; wire [31:0] w0, w1, w2, w3; reg [31:0] w_k0,w_k1,w_k2,w_k3; reg [127:0] text_in_r; reg [127:0] text_out; reg [7:0] sa00, sa01, sa02, sa03; reg [7:0] sa10, sa11, sa12, sa13; reg [7:0] sa20, sa21, sa22, sa23; reg [7:0] sa30, sa31, sa32, sa33; wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next; wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next; wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next; wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next; wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub; wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub; wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub; wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub; wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr; wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr; wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr; wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr; wire [7:0] sa00_ark, sa01_ark, sa02_ark, sa03_ark; wire [7:0] sa10_ark, sa11_ark, sa12_ark, sa13_ark; wire [7:0] sa20_ark, sa21_ark, sa22_ark, sa23_ark; wire [7:0] sa30_ark, sa31_ark, sa32_ark, sa33_ark; reg ld_r, done; reg [3:0] dcnt; reg go=0; //shangsheng 'go' always @(posedge clk) if(!rst) go <= #1 1'b0; else if(sel) go <= #1 1'b1; else if(done) go <= #1 1'b0; always @(posedge clk) if(!rst) dcnt <= #1 4'h0; else if(done) dcnt <= #1 4'h0; else if(ld) dcnt <= #1 4'h1; else if(go) dcnt <= #1 dcnt + 4'h1; always @(posedge clk) done <= #1 (dcnt==4'hb) & !ld; always @(posedge clk) if(ld) text_in_r <= #1 text_in; //read always @(posedge clk) l...
