下载后可任意编辑摘 要为了适应全数字化自动控制更加广泛的应用，采纳 FPGA 对 UART 进行多模块的系统设计的方法，使串口通信的集成度更高。对 UART 系统结构进行了多模块的分解。UART(通用异步收发器)是一种应用广泛的短距离串行传输接口，常用于短距离、低速、低成本的通信中。本文采纳 Verilog 语言设计了一个 UART发送模块和接收模块，从而可实现 FPGA 和 PC 机的异步串行通。利用 Altera 公司的 EP1C6Q240I8 芯片，采纳 Altium Designer Summer 09 画出原理图及 PCB图且在 QuartusII9.0 环境下进行设计、编译、仿真。关键字：UART，FPGA，Verilog，原理图，PCBI电子科技大学成都学院本科毕业设计论文 II下载后可任意编辑 ABSTRACTIn order to meet the full digital automatic control is used more and more widely, a systematic design method of FPGA module of UART, the serial communication, a higher degree of integration. The structure of UART system is decomposed multi module. UART (Universal Asynchronous Receiver Transmitter) is a short distance serial transmission interface is a widely used, communication used in short distance, low speed, low cost. This paper describes the design of a UART transmitting module and a receiving module using Verilog language, which can be asynchronous serial FPGA and PC machine implementation. Using EP1C6Q240I8 chip of Altera company, 09 draw the schematic diagram and PCB diagram and design, compile, simulation in QuartusII9.0 environment using Altium Designer Summer. Key Words: UART，FPGA，Verilog，Schematic diagram，PCB IIIABSTRACT 目 录第 1 章 引言 ......................................................... 0 1.1 课题任务 ........................................................ 0 1.2 课题要求 ........................................................ 1 1.3 讨论意义 ........................................................ 2 第 2 章 设计方案 ..................................................... 4 2.1 硬件部分 ...
