Paper ET3.1 INTERNATIONAL TEST CONFERENCE 1 978-1-4244-4867-8/09/$25.00 ©2009 IEEE Doing More with Less – An IEEE 1149.7 Embedded Tutorial : Standard for Reduced-pin and Enhanced-functionality Test Access Port and Boundary-Scan Architecture Adam W Ley ASSET InterTech, Inc. Richardson TX, USA Abstract IEEE Std 1149.7 offers a means to reduce chip pins dedicated to test (and debug) access while enhancing the functionality of the Test Access Port (TAP) as a complementary superset of the original IEEE Std 1149.1 (JTAG). Extended features such as hot-plug immunity, power management, optimization of scan throughput, access to instrumentation, and access to custom technologies provide welcome improvements for debug. Further, the boundary-scan architecture is bolstered to ensure full support for test. This important advancement in test and debug interfaces is well suited for access to multiple cores on SOC or multiple die in SIP or POP. 1. Introduction In the 1980s, the Joint Test Action Group (JTAG) was formed to address a growing concern about diminishing test access to chips on boards due to the adoption of surface-mount assembly methods and ongoing miniaturization of chip packages. In 1990, their efforts culminated in the ratification of IEEE Std 1149.1 – Standard Test Access Port and Boundary-Scan Architecture. While 1149.1 was firmly rooted in the need to solve the problems of board test, as exemplified by the provision for boundary scan, the proponents of the standard realized the need for a generalized means of low-level access to components on boards and in systems that would suit a wide range of uses. As a result, the 1149.1 test access port (TAP), as specified, has met this need. In fact, eve...
