毕业设计论文用 VHDL 语言设计数据采集系统摘要随着计算机技术的进展与普及，数字设备正越来越多地取代模拟设备，将模拟信号转换成数字信号以及将数字信号转换成模拟信号就成了重要环节。本系统以多路数据的采集及监测为例，介绍了可编程逻辑器件在模数转换、数模转换及数据监控及处理中的设计方法。实现数据采集的方法有很多，如单片机、CPLD、C 语言等，但相比各种方法，运用 VHDL 硬件描述语言开发的数据采集系统具有具有设计方便高效、体积小、功耗低、可靠性高、易于修改、设计周期短等特点。VHDL 硬件描述语言采纳自顶而下的设计方法可以对模型进行及时修改，以改进系统或子系统的功能，更正设计错误，从而提高目标系统的工作速度，减小面积耗用，降低功耗和成本等。本文介绍了基于Altera 公司的集成开发环境 MaxplusII，使用 VHDL 设计开发数据采集系统的基本方法。[关键词] VHDL ADC0809 DAC0832 EDA 数据采集； AbstractWith the development of computer technology and popularization, Digital devices are increasingly replacing analog equipment,and converted the analog signals into digital signals, as well as digital signal into analog signal will become an important link.for example,this syestem depend on one multi-channel data acquisition and monitoring,introduce a programmable logic device in the analog-digital conversion, digital-analog conversion and data monitoring with handling methods in the design. There are many ways to collect data, such as SCM, CPLD, C language,and so on. But compared with various methods,using the VHDL hardware description language to design the data acquisition system is the best. Because of its facilitate ,efficient, small size, low power consumption, high reliability, easy to modify, and shorter design cycle characteristics. VHDL hardware description language using the top-down design method ,that can be the model for timely changes to improve the system or subsystem functions, design error correction, so as to enhance the work o...
