数字计时器设计数字计时器设计 目 录一．实验内容简介 ····························3二．实验要求 ································3三．实验原理 ································4四．单元电路设计及其电路图 ··················41.秒信号发生器 ·····························42.计时电路 ·································53.清零电路··································74.校分电路 ································75.报时电路·································8五 ． 附 加 功 能 ： 起 停 原 理 及 电 路图·············10六．实验感想 ······························11七．附录 ·································111.工具及器件清单 ·························112各元件的引脚图及功能表 ·················133总电路逻辑图 ···························15（包含附加电路的总电路图附加在报告最后）八．参考文献 ·····························15一． 实验内容：本实验采纳中小规模集成电路设计一个由脉冲发生电路，计时电路，译码显示电路，和控制电路(包括清零电路，校分电路，和报时电路)等四部分组成的数字计时器。二． 设计要求：1.设计一个脉冲发生电路，为计时器提供秒脉冲、为报时电路提供驱动蜂鸣器的脉冲信号。2. 设计一个计时电路，完成 0 分 00 秒~9 分 59 秒的计时功能。3. 设计报时电路，使数字计时器从 9 分 53 秒开始报时，每隔一秒发一声，共发三声低音，一声高音；即 9 分 53 秒、9 分 55 秒、9 分 57 秒发低音（频率 1kHz），9 分 59 秒发高音（频率 2kHz）4. 设计校分电路，在任何时候，拨动校分开关，可进行快速校分。5．设计清零电路，具有开机自动清零功能，并且在任何时候，按动清零开关，可以进行计时器清零。6．系统级联调试，将以上电路进行级联完成计时器的所...
