Goke Microelectronics I ASIC 设计-FPGA 原型验证 版本 修改内容 修改人 时间 1.0 2014.07 1.1 2014.09 ASIC Design Team ASIC 设计-FPGA 原型验证 II 目录 1 ASIC 验证技术 ...................................................................................................... 1 1.1 ASIC设计流程 ............................................... 1 1.2 FPGA验证技术 ............................................... 3 1.3 Altera与Xilinx工具对比 .................................... 3 1.4 VHDL与Verilog对比 ......................................... 5 1.5 Verilog良好编程习惯 ........................................ 6 2 基于ALTERA 的ASIC 验证 ................................................................................. 9 2.1 Stratix IV FPGA资源与架构 .................................. 9 2.2 QuartusII设计工具 ......................................... 10 2.3 ASIC设计转换 .............................................. 11 2.3.1 PLL 设计 ............................................................................................ 11 2.3.1 RAM 设计 .......................................................................................... 16 2.4 时序约束 ................................................... 19 2.4.1 QSF&Tcl ............................................................................................. 22 2.4.2 LogicLock ........................................................................................... 23 2.5 综合布局布线 ............................................... 23 2.5.1 综合设置 ............................................................................................. 24 2.5.2 增量编译 ............................................................................................. 25 2.5.3 VQM & QXP ...................................................................................... 30 2.5.4 时序分析 .........................................................
