FPGA密码锁

按键程序： module key(code,scan,reset,en,clr,key0,key1,key2,key3,key4,key5); input scan,reset,en,clr,key0,key1,key2,key3,key4,key5; output [31:0]code; reg [31:0]code; always @(posedge scan or negedge clr or negedge en) begin if(!clr) begin code=0; end else begin if(!en) begin code=0; end else begin if(key5==0) begin code=4'b1111; end else begin code=4'b1110; end end end end Endmodule 控制程序： module kongzhi(reset,high_clk,clk,key0,key1,key2,key3,key4,key5,key6,key7,Q5,Q20,code,en5,clr5,en20,clr20,p_en,p_clr,red,green,alarm); input reset,high_clk,clk,key0,key1,key2,key3,key4,key5,key6,key7; input [2:0]Q5; input [4:0]Q20; input [31:0]code; output en5,clr5,en20,clr20,p_en,p_clr,red,green,alarm; reg en5,clr5,en20,clr20,p_en,p_clr,red,green,alarm; parameter [2:0]WAIT=3'h0,INPUT1=3'h1,INPUT2=3'h2,OPEN=3'h3,ALARM=3'h4,CHANGE=3'h5; reg [2:0]cur_state,next_state; reg [23:0]password; always @(negedge reset or posedge key7) begin if(!reset) password<=24'd12345678; else if(cur_state==CHANGE) password<=code; end always @(posedge clk or negedge reset) begin if(!reset) cur_state<=WAIT; else cur_state<=next_state;//cur_state<=next_state; end always @(cur_state or key0 or key1 or key2 or key3 or key4 or key5 or key6 or key7 or Q5 or Q20) begin case(cur_state) WAIT: begin if(!key6) next_state<=INPUT1; else next_state<=cur_state; end INPUT1: begin if(Q5>=5) next_state<=ALARM; else if((!key0)||(!key1)||(!key2)||(!key3)||(!key4)) next_state<=INPUT2; else next_state<=cur_state; end INPUT2: begin if(!key7) begin if(code==password) next_state<=OPEN; else next_state<=ALARM; end else next_state<=cur_state; end OPEN: begin if(!key5) next_state<=WAIT; else if(!key6) next_state<=CHANGE; else next_state<=cur_state; end ALARM: begin if(Q20>=20) next_state<=WAIT; else next_state<=cur_state; end CHANGE: begin if((!key6)||(!key7)) next...