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Appendix D: ImplementingState Machines using VerilogBehavioural ModeD.1INTRODUCTIONIn Chapters 1–5, state machines have been implemented using the equations obtained from thestate diagram. This approach ensures that the logic for the state machine is under completecontrol of the designer.However, if the state machine is implemented using behavioural mode, the Verilog compilerwill optimize the design.There is a very close relationship between the state diagram and the behavioural Verilogdescription that allows a direct translation from the state diagram to the Verilog code.D.2THE SINGLE-PULSE/MULTIPLE-PULSE GENERATOR WITH MEMORYFINITE-STATE MACHINE REVISITEDIn this system there are two inputs: s to start the system and x to choose either single-pulse ormultiple-pulsemode.Insingle-pulsemode,theLouputisusedtoindicatetotheuserthatasinglepulse has been generated. In multiple-pulse mode, L is suppressed. Figure D.1 illustrates thestate diagram for this system.Rather than derive the equations directly from the state diagram, a Verilog description can beobtained directly from the state diagram of Figure D.1. This is illustrated in Listing D.1.// Behavioural State Machine.module pulsar(s,clk,rst,P,L,ab);1input s,clk,rst;2output [1:0]ab,P,L;3reg [1:0]state, P, L;4parameter s0¼2’b00, s1¼2’b01, s2¼2’b11, s3¼2’b10;// now define state sequence for FSM (from state diagram).5always @ (posedge clk or negedge rst)6if (�rst)7state <¼ s0;FSM-based Digital Design using Verilog HDL Peter Minns and Ian Elliott# 2008 John Wiley & Sons, Ltd. ISBN: 978-0-470-06070-48else9case(state)10s0: if (s) state <¼s1; else state <¼ s0;11s1: state <¼ s2;12s2: if (�x) state <¼ s3; else state <¼ s1;13s3: if (�s) state <¼s0; else state <¼ s3;14endcase// now define...