乐曲硬件演奏电路的 VHDL 设计1.Songer 顶层文件模块: LIBRARY IEEE; -- 硬件演奏电路顶层设计 USE IEEE.STD_LOGIC_1164.ALL; ENTITY Songer IS PORT ( CLK4MHZ : IN STD_LOGIC; --音调频率信号 CLK8HZ : IN STD_LOGIC; --节拍频率信号 pause: IN STD_LOGIC; CODE1 : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);-- 简谱码输出显示 HIGH1 : OUT STD_LOGIC; --高 8 度指示 SPKOUT : OUT STD_LOGIC );--声音输出 END; ARCHITECTURE one OF Songer IS COMPONENT NoteTabs PORT ( clk : IN STD_LOGIC; SWITCH: IN STD_LOGIC; ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END COMPONENT; COMPONENT ToneTaba PORT ( Index : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ; CODE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ; HIGH : OUT STD_LOGIC; Tone : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) ); END COMPONENT; COMPONENT Speakera PORT ( clk : IN STD_LOGIC; Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0); SpkS : OUT STD_LOGIC ); END COMPONENT; SIGNAL Tone : STD_LOGIC_VECTOR (10 DOWNTO 0); SIGNAL ToneIndex : STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN u1 : NoteTabs PORT MAP (clk=>CLK8HZ, SWITCH=>pause,ToneIndex=>ToneIndex); u2 : ToneTaba PORT MAP (Index=>ToneIndex,Tone=>Tone,CODE=>CODE1,HIGH=>HIGH1); u3 : Speakera PORT MAP(clk=>CLK4MHZ,Tone=>Tone, SpkS=>SPKOUT ); END; 2.音乐节拍和音调发生器（NoteTabs.VHD） LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY NoteTabs IS PORT ( clk : IN STD_LOGIC; switch: IN STD_LOGIC; ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END; ARCHITECTURE one OF NoteTabs IS COMPONENT MUSIC --音符数据 ROM PORT(address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END COMPONENT; SIGNAL Counter : STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN CNT8 : PROCESS(clk,Counter) BEGIN IF Counter=138 THEN Counter Counter , q=>ToneIndex, inclock=>clk); END; 3.简谱码对应的分频预置数查表电路（ToneTaba.VHD） LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ToneTaba IS PORT ( Index : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ; CODE : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ; HIGH : OUT STD_LOGIC; Tone : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) ); END; ARCHITECTURE one OF ToneTaba IS BEGIN Search : PROCESS(Index) BEGIN CASE Index IS -- 译码电路，查表方式，控制音调的预置数 WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN OTHERS => NULL; END CASE; END PROCESS; END; 4.数控分频与演奏发生器（Speakera.VHD） LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Speakera IS PORT ( clk : IN STD_LOGIC; Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0); SpkS : OUT STD_LOGIC ); END; ARCHITECTURE one OF Speakera IS SIGNAL PreCLK, FullSpkS : STD_LOGIC; BEGIN DivideCLK : PROCESS(clk) VARIABLE Count4 : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PreCLK 11 THEN PreCLK
