幻灯片 1幻灯片 2幻灯片 3幻灯片 4幻灯片 5幻灯片 6幻灯片 7幻灯片 8幻灯片 9幻灯片 10幻灯片 11幻灯片 12幻灯片 13幻灯片 14幻灯片 15幻灯片 16幻灯片 17幻灯片 18幻灯片 19幻灯片 20幻灯片 21幻灯片 22幻灯片 23幻灯片 24幻灯片 25幻灯片 26幻灯片 27幻灯片 28幻灯片 29幻灯片 30幻灯片 31幻灯片 32幻灯片 33幻灯片 34幻灯片 35Primary difference between the two implementations (at this level) are:The Intel processor has a smaller L1 but larger L2 caches
Shared L2 cache vs
separateShared cache allows a larger cache to be available to one core if it needs it (and assumes the other core does not need it)
This is dynamic allocation of the cache resource
Integrated memory controller vs
non-integratedThe presence of the System Request Interface, Cross bar, and the high-speed serial interface (HyperTransport) are all logical results of having an integrated memory controllerIt is difficult to say which implementation