集成电路课程设计实习内容VIP免费

集成电路课程设计7月15~25日：集成电路课程设计7月26~28日：撰写课程设计报告集成电路课程设计题目1.DESIGNFLIP-FLOP2.DESIGNACMOS8-BITALU3.DESIGNACMOS8-BITACCUMULATOR4.DESIGNACMOS8-BITMULTIPLIER5.DESIGNA8-BITBIDIRECTIONALSHIFTREGISTER6.DESIGNASYNCHRONOUS8-BITUPANDDOWNCOUNTER1必做（已做），2~6选作1个或自拟题目集成电路课程设计APseudo-RandomCodeGenerator8-bitbinarydividerCRC(cyclicredundancychecker).7x4SignedParallelDivisionCircuitAutomobileLockingControlSystemProgrammablecounter参考电路DFFALUFULLADDERN-BITADDERMULTIPLIERDFFDFFDFFM1DQM3CLKM4M2CLKVDDCL1XCL2MasterStageM5M7CLKCLKM8M6VDDCC22MOSMOSDFFCLKCLKDVDDM3M2M1CLKYVDDQQM9M8M7CLKXVDDM6M5M4TSPCRegisterTSPCRegisterALU44444AULUMUXABF01SC-1C3S0S1S2FullAdderFULLADDERSCHEMATICComplimentaryStaticCMOSFullAdderComplimentaryStaticCMOSFullAdderFULLADDERSCHEMATICTheMirrorAdderTheMirrorAdderCMOSTGFullAdderCircuitSumCoutABCinnp-CMOSAdderCircuitB0C0C0C0!C1!Sum0B0A0A0B0B0A0A0CLKCLK!CLK!CLKC2Sum1!A1!A1!B1!B1!A1!A1!B1!B1!C1!C1!CLK!CLKCLKCLK1x0x0x1x0x0x1x1xN-bitAdderFAFAFAFAA0B0S0A1B1S1A2B2S2A3B3S3Ci,0Co,0(Ci,1)Co,1Co,2TheRipple-CarryAdderTheRipple-CarryAdderN-bitAdder超前进位加法器（进位逻辑）N-bitAdderRipple-CarryAdderRipple-CarryAdderLookAheadCarry-BypassAdderCarry-SelectAdderMULTIPLIERY0Y1X3X2X1X0X3HAX2FAX1FAX0HAY2X3FAX2FAX1FAX0HAZ1Z3Z6Z7Z5Z4Y3X3FAX2FAX1FAX0HATheArrayMultiplierTheArrayMultiplierMULTIPLIERHAHAHAHAFAFAFAHAFAHAFAFAFAHAFAHAVectorMergingAdderCarry-SaveMultiplierCarry-SaveMultiplierHowtoGetStartedFindrelevantreadingmaterials.DevelopasetofspecificationsthatmeettherequirementsofthechosenapplicationMakeahighlevelroughsketchDivideandconquerMakeascheduleandsticktoit课程设计报告要求摘要选题意义、背景，基本理论，方案选择设计详细内容ASIC设计流程代码描述及仿真向量仿真验证（VerilogXL或NC-lanch）逻辑综合布局布线版图生成DRC，EXTRACT，LVS定制设计流程电路原理及电路设计电路仿真验证（VerilogXL或NC-lanch）版图设计DRC，EXTRACT，LVS最高工作频率分析结论（功能、面积、功耗、延时）SomeFinalTipsStartearly;don’tleaveanythinguntillastminute.Periodicallysavebackups.Keeptrackofwhatneedstobeturnedinasyougoalong.SomeDesignTipsMakeeverythingmodular,andtestoftenateverystep.Trytokeepeverythingastandardrectangularshape,includingfinaldesign.UsingEulerpathstocreateefficientlayoutsforcomplexgatesisbetterthanstringingtogethermanysimplegates.Alwayskeepinmindbigpicture.HowamIgoingtorouteinputs/powertoeachblockinthefinallayout?UsewideVddandGndlines,routetheselines(andothers,likeclock)efficiently.Don’troutepolyoveralongdistance.