表 1 拨动开关引脚配置 Signal Name FPGA Pin No
Description I/O Standard SW[0] PIN_AB28 Slide Sw itch[0] Depending on JP7 SW[1] PIN_AC28 Slide Sw itch[1] Depending on JP7 SW[2] PIN_AC27 Slide Sw itch[2] Depending on JP7 SW[3] PIN_AD27 Slide Sw itch[3] Depending on JP7 SW[4] PIN_AB27 Slide Sw itch[4] Depending on JP7 SW[5] PIN_AC26 Slide Sw itch[5] Depending on JP7 SW[6] PIN_AD26 Slide Sw itch[6] Depending on JP7 SW[7] PIN_AB26 Slide Sw itch[7] Depending on JP7 SW[8] PIN_AC25 Slide Sw itch[8] Depending on JP7 SW[9] PIN_AB25 Slide Sw itch[9] Depending on JP7 SW[10] PIN_AC24 Slide Sw itch[10] Depending on JP7 SW[11] PIN_AB24 Slide Sw itch[11] Depending on JP7 SW[12] PIN_AB23 Slide Sw itch[12] Depending on JP7 SW[13] PIN_AA24 Slide Depending on Sw itch[13] JP7 SW[14] PIN_AA23 Slide Sw itch[14] Depending