TN-04-56: Dealing with DDR2/DDR3 Clock JitterIntroductionSource: 09005aef836b5f34Micron Technology, Inc., reserves the right to change products or specifications without notice.TN0456_fm - Rev. A 11/08 EN1©2008 Micron Technology, Inc. All rights reserved.Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All information discussed herein is provided on an “ as is” basis, without warranties of any kind. Technical NoteDesign Guide – Dealing with DDR2/DDR3 Clock JitterIntroductionPrior to DDR2 technology, the expectation was that clock jitter specifications could be absorbed by the DRAM timing specifications. DDR2’s faster clock rates and on-chip delay locked loop (DLL) changed all that, and industry-standard clock jitter specifica-tions became a requirement for users and suppliers. Micron, however, actually started specifying clock jitter specifications with the release of DDR memory. Despite the fact that there seemed to be enough timing margin with DDR, the inclusion of the DLL begged for clock jitter guidance. Now, even though both DDR2 and DDR3 have clock jitter specifications, few DRAM users understand how to apply them or how to deter-mine if their system clock violates the specification limits and what action to take if it does.This design guide explores DDR2/DDR3 clock jitter specifications and provides guid-ance on how to apply them and how to deal with violations since many systems will unintentionally encounter them. (Note that statements made are equally applicable to DDR2 and DDR3 SDRAM, unless stated otherwise.)Definin...
