Verilog-按键消抖程序

Verilog-按键消抖程序(9页)Good is good, but better carries it.精益求精，善益求善。 按键消抖一、 程序（50mhz）module xiaodou(clk,clr,key1,key2,key3,key4,key5,key_out1,key_out2,key_out3,key_out4,key_out5);input clk,clr;input key1,key2,key3,key4,key5;output key_out1,key_out2,key_out3,key_out4,key_out5;//-------------------------------------------------reg [4:0] key_rst;reg [4:0] key_rst_n;reg [19:0] cnt;reg [4:0] key_next;reg [4:0] key_next_n;reg d1,d2,d3,d4,d5;wire[4:0] key_flag;wire [4:0] key_out_n;reg [23:0] count1;reg count_flag;always @(posedge clk or negedge clr) //get the fist valuebegin if(!clr)begin key_rst<=5'b11111;endelse begin key_rst<={key5,key4,key3,key2,key1};endend//--------------------------------------- always @(posedge clk or negedge clr)begin if(!clr)begin key_rst_n<=5'b11111;endelse begin key_rst_n<=key_rst;endend//----------------------------------------assign key_flag=key_rst_n&(~key_rst);//--------------jishu-------------------always @(posedge clk or negedge clr)beginif(!clr)begin cnt<=20'd0;endelse if(key_flag)begin cnt<=20'b0;end else begin cnt<=cnt+1'b1;endend//-----------------20ms after -------------always @(posedge clk or negedge clr)beginif(!clr)begin key_next<=5'b11111;endelse if(cnt==20'hfffff)begin key_next<={key5,key4,key3,key2,key1};endend//----------------------------------always @(posedge clk or negedge clr)beginif(!clr)begin key_next_n<=5'b11111;endelse begin key_next_n<=key_next;endend//-------------------------------------------assign key_out_n=key_next_n&(~key_next);//--------------------------------------always @(posedge clk or negedge clr)begin if(!clr)begin d1<=1'b1; d2<=1'b1; d3<=1'b1; d4<=1'b1; d5<=1'b1; count_flag<=1;endelse //应 led 止显示一个时钟周期，我们观测不到，begin //此处有个计数延时，目的是led 灯显示能够持续一段时间if(key_out_n[0]) begin d1<=1'b0;count_flag<=1'b0;end else if(count1==24'hffffff) begin d1<=1'b1;count_flag<=1;endif(key_out_n[1]) begin d2<=1'b0;count_flag<=1'b0;end else if(count1==24'hffffff) begin d2<=1'b1;count_flag<=1;endif(key_out_n[2]) begin d3<=1'b0;count_flag<=1'b0;end else if(count1==24'hffffff) begin d3<=1'b1;count_flag<=1;endif(key_out_n[3]) begin d4<=1'b0;count_flag<=1'b0;end else if(count1==24'hffffff) begin d4<=1'b1;count_flag<=1;endif(key_out_n[4]) begin d5<=1'b0;count_flag<=1'b0;end else if(count1==24'hffffff) begin d5<=1'b1;count_flag<=1;endendendassign key_out1=d1?1'b1:1'b0;assign key_out2=d2?1'b1:1'b0;assign key_out3=d3?1'b1:1'b0;assign key_out4=d4?1'b1:1'b0;assign key_out5=d5?1'b1:1'b0;always @(posedge clk or negedge clr) //计数延时，具体时间没有计算beginif(!clr)begin count1<=0;endelse if(count_flag==1'b0)begin count1<=count1+1'b1;endelse begin count1<=0;endendendmodule二、 框图:…。^|【$`^`：':…！《%》{,%$"$：？（、！*